The present invention relates to a method of reducing waiting time jitter that results when pulse stuffing is employed for the transmission of digital signals.
If a given digital signal is to be transmitted at a bit rate other than its original bit rate, the method of pulse stuffing is employed. This method is employed particularly if plesiochronous signals are bundled in time multiplex in multiplexing devices, with a demultiplexer performing the inverse function. Pulse stuffing may also be employed if, for example for the purpose of synchronization, a signal at a first bit rate is imaged in a switching frame at a second, higher bit rate. This imaging, which is usually performed according to a specific rule, will hereinafter be called mapping and the inverse process demapping.
Essentially two pulse stuffing variations are known: positive stuffing and positive-zero-negative stuffing. For demultiplexing or demapping, the stuffing process must be reversed again to enable the original digital signal to be recovered. An important point is here the recovery of the clock. During this recovery, the clock is smoothed only incompletely. It differs from the original clock by a phase modulation, the jitter. The waiting time jitter is a low frequency phase jitter which, in principle, occurs whenever asynchronous digital signals are synchronized by means of pulse stuffing.
The article by D. L. Duttweiler, entitled "Waiting Time Jitter", published in Bell System Technical Journal, Vol. 51, No. 1, 1972, pages 165-207, and incorporated herein by reference, discloses a derivation of waiting time jitter and experimental data regarding the spectrum of the waiting time jitter. A synchronizer and a desynchronizer for positive stuffing are described.
The article by F. Kuhne and K. Lang, entitled "Positiv-Null-Negativ-Stopftechnik fur Multiplexubertragung plesio-chroner Datensignale" (Positive-Zero-Negative Stuffing Technique for Multiplex Transmission of Plesiochronous Data Signals) published in Frequency, Volume 32, No. 10, 1978, pages 281-287, and incorporated herein by reference, discusses waiting time jitter during positive-zero-negative stuffing. This publication discloses the writing of an input signal D with a clock T into an elastic memory of a synchronizer, with the addressing being effected by means of a counter Z1 which counts at a clock rate of the clock T. In a control circuit, a read-out signal is generated which acts on a counter Z2 to address the elastic memory for read-out. A phase comparator P compares the outputs of the counters Z1 and Z2. The phase difference is a measure of the fill level of the elastic memory. If this phase difference exceeds or falls below an upper or lower threshold, respectively, a stuffing process is performed at the next stuffing opportunity. The procedures for recovery of the signal D are essentially inverse. The desynchronizer is also provided with two counters and a phase comparator. As long as no stuffing takes place, the clock of the main channel of the input signal is employed as the read-out clock. After a stuffing process, a clock which is somewhat slower or somewhat faster is switched in as the read-out clock for an interval of compensation.
The problem of waiting time jitter during positive-zero stuffing and how to reduce it are discussed by W. D. Grover, T. E. Moore and J. A. McEachern in an article, entitled "Waiting Time Jitter Reduction by Synchronizer Stuff Threshold Modulation", published in GLOBECOM, 1987, 13.7.1, pages 514-518, and incorporated herein by reference. To reduce waiting time jitter, additional stuffing processes are provided for in the synchronizer, with these additional stuffing processes occurring in such a sequence that the effect is a frequency shift of the jitter. To employ this method, it is merely necessary to provide a new control in the synchronizer to determine when stuffing is to take place. While in the past stuffing took place only if a constant threshold were exceeded or not reached, in a process according to Grover, Moore and McEachen, the thresholds are modulated.
A prior synchronizer and desynchronizer, and the associated stuffing method, will be described with reference to FIGS. 1 and 2. The input signal to the synchronizer is a signal D consisting of a stream of bits arriving at a bit rate corresponding to the clock rate of a clock T. The output signal of the synchronizer is composed of a main signal D' and an auxiliary channel D". The original signal D is stored in an elastic memory ES. The elastic memory ES is addressed by means of a write-in counter Z1 counting at the clock rate of the clock T. A read-out clock signal with which the data are read out of elastic memory ES is generated in a control unit S and fed to a read-out counter Z2. If the average bit rates of the signals D and D' deviate from one another, stuffing processes are necessary. A phase comparator P compares the phases of the write-in counter Z1 with those of the read-out counter Z2. If the phase difference deviates from the desired value by a certain amount, control circuit S initiates a stuffing process. If positive stuffing is employed, a stuffing bit (dummy bit) is transferred into the signal D' at a defined location. If negative stuffing is employed, an additional information bit from the elastic memory is transmitted in the auxiliary channel D". The information as to whether a useful information bit or a stuffing bit is being transmitted during a stuffable time period (at a positive stuffing location), or whether an information bit is transmitted in the auxiliary channel D" (at a negative stuffing location), is transmitted at defined time intervals in the auxiliary channel D" and are the so-called stuffing information bits of auxiliary channel D".
Signals D' and D" are combined in a frame to form a signal A and are transmitted.
The input signals of the desynchronizer are the main signal D' and the auxiliary channel D". The output signal is the recovered data signal D* which differs from the synchronizer input signal in that it exhibits waiting time jitter. The procedures for data recovery in the desynchronizer are essentially the reverse of those performed in the synchronizer, as are the described adaptation procedures. If a code word evaluator CA determines on the basis of the stuffing information bits that stuffing did take place, a control circuit S' either puts out an additional pulse so that the counter Z1' writes the information bit I received in auxiliary channel D" into elastic memory ES' (follows the negative stuffing procedure) or the control circuit S' through the counter Z1' suppresses a clock pulse so that the stuffing bit of the signal D' is not written into the elastic memory (follows the positive stuffing procedure). For example, a phase locked loop circuit, including a phase comparator P', a filter F and a voltage controlled oscillator VCO, may be provided to recover the read-out clock signal which actuates read-out counter Z2'. In the phase locked loop circuit, the phase of write-in counter Z1' is compared with the phase of read-out counter Z2', the filter F is employed to filter an output signal of the phase comparator P' and the filtered signal is fed to the voltage controlled oscillator VCO which generates the read-out clock signal.
The measured difference between the phases of the write-in counter Z1 and the read-out counter Z2 corresponds to the fill level of elastic memory ES. Phase information regarding the relative phases of the original signal D and the main output signal D'--given by the change in the average fill level of the elastic memory ES--can be transmitted from the synchronizer to the desynchronizer only in 1-bit steps by means of the stuffing information. When using the conventional positive-zero-negative stuffing procedure, this method of transmitting phase information produces a high waiting time jitter.